A novel on-chip delay measurement hardware for efficient speed-binning

Abstract

With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, speed binning of the high performance VLSI chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, the authors have proposed a novel on-chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-chip speed binning.