On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

Abstract

This paper presents techniques for measurement and compensation of timing variations in clock and data channels of source-synchronous high-speed serial network-on-chip (NoC) links. Timing mismatch measurements are performed by means of asynchronous sub-sampling. This allows the use of low quality sampling clocks to reduce test hardware overhead for integration into complex MPSoCs (Multiprocessor System-on-Chip) with multiple NoC links. The effect of clock jitter on the measurement results is evaluated. Delay mismatch is compensated by tunable delay cells. The proposed technique enables compensation of delay variations to realize high-speed NoC links with sufficient yield. It is demonstrated at NoC links as part of an MPSoC in 65 nm Complementary Metal Oxide Semiconductor technology, where the calibration significantly reduces bit-error-rates of a 72 GBit/s (8 GBit/s per lane) link over 4 mm on-chip interconnect.