Abstract
Abstract Although the recently developed reduced instruction set computer (RISC) architecture has proven to offer impressive performance in general applications, it has its drawbacks in the field of multitasking real-time environments. The difficulties are mainly related to the large number of processor registers which must be saved and restored on every context switch. On the other hand, since this large number of registers accounts for most of the performance benefits, a concept had to be developed which preserves the advantages of the RISC architecture and provides for the necessary real-time capabilities. This paper describes a solution in which additional hardware performs a part of the save/restore task associated with every context switch. This approach yields a RISC architecture suited for the requirements of a modern process control system. Subject area. 4.1 Digital Computer Control Systems
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