Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS

Abstract

In the design of nonvolatile memory (NVM), the sensing scheme (SS) has become a read-energy bottleneck because the required read-cell current is too large to satisfy a target read yield. This problem is further aggravated by technology scaling because increased process variation and reduced supply voltage ( $V_{\mathrm {DD}}$ ) require more current to satisfy the target read yield. This paper proposes an offset-canceling single-ended SS (OCSE-SS) with one-bit-line precharge architecture (1BLPA) that is intended for use in ultralow power NVM applications. The test chip is fabricated using 65-nm process technology, and the measurement results show that the read energy per bit of the OCSE-SS is 1/3 compared to that of the conventional SS (Conv-SS). The read energy reduction comes from the single-ended sensing, offset cancellation, and 1BLPA features. Moreover, when a resistance difference between the data and reference cells is as small as $0.5~k\Omega $ , the OCSE-SS reads successfully with a $V_{\mathrm {DD}}$ of 1.0 V and a sensing time ( $t_{\mathrm {SEN}}$ ) of 17 ns due to the offset cancellation characteristic, whereas the Conv-SS fails regardless of $V_{\mathrm {DD}}$ and $t_{\mathrm {SEN}}$ values.