Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level

Abstract

In deep-sub-micron technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis. This paper proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study yield of a dynamic-NOR using static keeper. The analytical formulations can be extended to a wide range of dynamic gates (for example pre-charge dynamic gates using dynamic keeper) because we use numerical approach for the calculation of derivatives required by error propagation. The proposed methodology presents errors less than 2% as compared to Monte Carlo simulation, while increasing computational efficiency up to 50×.