Observation of current staircase due to large quantum level spacing in a silicon single-electron transistor with low parasitic series resistance

Abstract

We have fabricated a silicon point-contact channel single-electron transistor (SET) with an ultrasmall dot. By narrowing only the point-contact region and suppressing the parasitic series resistance, a peak conductance as large as 8.8 μS and single-electron addition energy as large as 128 meV are simultaneously obtained. A current staircase due to the large quantum level spacing is clearly observed at low temperatures. From numerical calculations, it is found that the staircase feature due to discrete quantum levels stands out even at room temperature in future silicon SETs with an ultrasmall dot.