Abstract
In this paper, performances of a 4H-SiC UMOSFET with split gate and P+ shielding in different configurations are simulated and compared, with an emphasis on the switching characteristics and short circuit capability. A novel structure with the split gate in touch with the P+ shielding is proposed. The key design issues for 4H-SiC UMOSFETs are trench gate dielectric protection and reverse transfer capacitance Crss reduction. Based on simulation results, it is concluded that a UMOSFET with a gate structure combining split gate grounded to the trench bottom protection P+ shielding layer and a current spreading layer is achieved to yield the best compromise between conduction, switching, and short circuit performance. The split-gate design can effectively reduce Crss by shielding the coupling between the gate electrode and the drain region. The P+ shielding design not only protects the oxide at trench bottom corners but also minimizes the short channel effect due to drain-induced barrier lowing and the channel length modulation. Trade-off of the doping concentration of current spreading layer for UMOSFET is also discussed. A heavily doped current spreading layer may increase Crss and influence the switching time, even though RON,SP is reduced.
Highlights
SiC-based devices are promising candidates as power switches in various applications, thanks to the superior material properties of SiC, especially the wide bandgap, high critical electrical field, and excellent thermal conductivity [1]
To circumvent the drawbacks brought by the low electron channel mobility, many approaches with different gate structures have been proposed, and among them, the trench gate MOSFET (UMOSFET) is very promising
In order to take advantage of UMOSFETs for high cell density, the cell pitch is fixed to be 3.5 μm, which is smaller than state-of-the-art 4H-SiC DMOSFETs
Summary
SiC-based devices are promising candidates as power switches in various applications, thanks to the superior material properties of SiC, especially the wide bandgap, high critical electrical field, and excellent thermal conductivity [1]. Energies 2020, 13, 1122 to add a P+ shielding (PS) region at the bottom of the trench gate, so the electric field in the oxide at the trench gate corner can be reduced significantly [9,10] Such a design can introduce a parasitic JFET resistance along the current path and may require a current spreading layer to reduce it. Another important issue in the design of UMOSFETs is the large gate-to-drain capacitance (Cgd) which comes from the large cell density. A new design is suggested, which can retain the advantages of conventional UMOSFETs such as low RON,SP and high blocking voltage, and minimize the electric field in the oxide at the trench gate corner and possess a superior short-circuit capability
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