Numerical simulation on novel nano-scale lateral double-gate tunneling field effect transistor

Abstract

A novel nano-scale lateral double-gate tunneling field effect transistor (LDG-TFET) is proposed in this paper and its performance is shown through two dimensional device numerical simulations. The study result demonstrates that this new tunneling transistor allows for the steeper sub-threshold swings, e.g. below 60 mV/Dec, the super low supply voltage, e.g. operable at VDD ≪0.2V and the high ratio between the turn-on and turn-off current for the availability of high-k/metal stack materials. This tunneling field effect transistor may be integrated with present CMOS process and architecture with some specific applications such as memories because of the low turn-off current and when the delay is truly determined by interconnects because of its high turn-on/turn off ratio, which are important for next generation of micro-power and ultra-low integrated circuits.