Numerical evaluation of the ITRS transistor scaling

Abstract

Predictions of the ITRS were evaluated using state-of-the-art numerical TCAD simulations. For this purpose, first a physically based simulation model was calibrated to reproduce published experimental results for CMOS transistors with a gate length of 20 nm. Then, the same physical model was applied for the numerical simulation of CMOS devices as specified by the ITRS for the years 2011---2026 with physical gate lengths scaled from 24 to 5.9 nm. Simulations of this work indicate that the quantum electron depletion at the interface between the silicon and the gate oxide strongly limits the CMOS transistor performance. To compensate the negative impact of the quantum depletion effect, a more aggressive gate-oxide scaling is suggested.