Numerical comparisons of the operational degradation of ferroelectric field-effect transistors using Hf–Zr–O thin films by charge pumping technique

Abstract

From the viewpoint of interface quality within the gate stack, it is crucial to accurately evaluate the device performance of ferroelectric field-effect transistors (FeFETs). In this article, a measurement scheme composed of pulse configurations is designed to avoid dynamic changes in the threshold voltage of the FeFET during charge pumping (CP) measurements. Three types of control devices experiencing different levels of bias stress are prepared for investigations of the origins of device performance degradation. The frequency dependence of applied voltage levels to induce variations in CP current (I CP) are suggested to result from charge-injection events into deteriorated interface trap sites. These behaviors were also verified by the pulsed current–voltage (I–V) method using high-frequency gate voltage (V GS). The frequency dispersion of memory window (MW) variations and their V GS-sweep polarity dependences well reflect the interfacial behavior related to the charge injection of the stressed devices. The trap/detrap times and locations of trapped charges are examined by the energy distribution of trap sites calculated from the obtained I CP values. Thus, the MW obtained from the FeFET should be accurately analyzed to separate the charge-injection components from ferroelectric field effects by means of the proposed useful guidelines using the CP and pulsed I–V methods.