Numerical and experimental study on Cu protrusion of Cu-filled through-silicon vias (TSV)

Abstract

Three-dimensional integrated circuit (3DIC) technologies are receiving attention due to several advantages such as multi-function, low form factor and high performance microchip. Through-silicon via (TSV) approach is essential for 3DIC packaging technology. TSV fabrication process, however, is still facing several challenges. One of the widely-known challenges is via protrusion. Annealing a silicon wafer makes the Cu TSVs inside are under high stress and may form a protrusion where the Cu is forced out of the blind TSV. This phenomenon occurred because the large mismatch in the Coefficient of Thermal Expansion (CTE) between Copper (Cu) vias and Silicon (Si) surrounding it. Cu protrusion can lead to crack or delamination of the Back End of Line (BEOL), thus, it is a risky threat to the metal layer interconnect and RDL structure. In this work, Finite Element Analysis (FEA) was carried out to study the Cu protrusion under different annealing temperatures. Experimental data were collected to characterize the protrusion using several techniques. Scanning Electron Microscope (SEM) and Atomic Force Microscope (AFM) were used to observe the protrusion shape and measure the height. Electron Backscatter Diffraction (EBSD) technique was done to study the grain size distribution and evolution inside Cu vias. For the experiment, arrays of 5 μm TSVs were fabricated and annealed in Nitrogen gas environment in different temperatures. Correlation between numerical results and experimental data was then carried out. Based on the verified FEA methodology, several parametric studies were then conducted including the effect of via diameter, depth, pitch, annealing temperature and duration on Cu protrusion. The simulation results help to understand and solve the key problem in TSV fabrication process and reliability challenge.