Abstract
The effects of back channel interfacial states (N bit ) that can be generated by passivation layer deposition for amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) by using an ATLAS 2D device simulator are analysed. As N bit is increased, the positive shift of threshold voltage (V TH ) is observed for thin and thick active layer TFTs due to the acceptor-like characteristics of interfacial states. However, as N bit is further increased, the V TH shift of the thick active layer TFT is eventually saturated, while that of the thin active layer TFT is continuously increased. This is because the characteristics of the a-IGZO TFT with a thin active layer are strongly affected by N bit , which can be used for optimising the performance of a-IGZO TFTs.
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