Numerical analysis of bonding process-induced deformation for 3D package

Abstract

Three-dimensional integrated packaging has been generally acknowledged as the next generation semiconductor technology with the advantages of small form factor, high-performance, low power consumption, and high density integration [1,2]. Through silicon via (TSV) and stacked bonding are the core technologies to perform vertical interconnect for 3D packaging. One of the most important topics in 3D packaging is the bonding alignment accuracy. It is reported that via diameters will continue to shrink over the next couple of years [3]. Shrinking via diameters have a direct effect on the post bond alignment accuracy that is required. There is always a minimum overlap requirement so that copper vias have good electrical connection with minimized resistance. However, warpage and high stress are introduced during bonding process leading to the misalignment between two chips being bonded and failure of the chips. Large misalignment will lead to the decrease of the bonding strength and consequently create the electrical connection problems. The coefficient of thermal expansion (CTE) of copper is much higher than that of silicon. And the CTE of the filling material between the silicon dies is generally higher than copper. The presence of package materials with different coefficients of thermal expansion will induce thermal expansion mismatch, which leads to very large stresses and deformation between package materials during fabrication process. In this paper, a finite element approach is proposed to predict the war-pages and stresses during the bonding process. The birth and death approach is used to predict the stress and war-page in one process to the next so that a full evolution of the warpage and stress during bonding can be obtained.