NTB branch predictor: dynamic branch predictor for high-performance embedded processors

Abstract

Branch prediction accuracy becomes more crucial in high-performance embedded processors. The importance of branch prediction in embedded processors continues to grow in the future. Many branch predictors have been proposed to alleviate the performance penalty due to branch mispredictions. However, recent embedded processors still have problems in increasing the branch prediction accuracy. This paper proposes number of taken branch instructions (NTB) branch predictor, a new dynamic branch predictor for high-performance embedded processors. The NTB branch predictor utilizes two-bit saturating counters in the pattern history table based on the information about the number of taken-branches in the global branch history. The proposed NTB branch predictor achieves improved accuracy by making use of longer branch history with no hardware overhead, because hardware resources for the proposed NTB branch predictor are independent of the history length. By contrast, existing dynamic branch prediction schemes require more hardware resources as the history length increases. According to our experiments with a 4 KB branch predictor which suits embedded processors, the NTB branch predictor improves the prediction accuracy by 7.11 and 43.41 % on average over the perceptron predictor and the two-level adaptive branch predictor, respectively.