Abstract
A new concept in general purpose digital signal processor (DSP) design will be proposed which makes it possible to exhibit the advantages of algorithms optimized for minimum number of addition operations. The proposed architecture is specified by an N-port arithmetic unit and N separate memories. The avoidance of all memory conflicts while the memories are simultaneously bandwidth limited, is discussed. It is shown how moderate control and overhead circuitry can be found. Further a discussion about the optimal choice of the arithmetic unit is given. Examples are presented comparing the use of wave digital (Fettweis) implementations and more conventional implementations of fixed point digital filters.
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