Novel Void Embedded Design for Total Ionizing Dose Hardening of Silicon-on-Insulator MOSFET

Abstract

A novel methodology for total ionizing dose (TID) hardening of Silicon-on-insulator (SOI) MOSFET is demonstrated by employing a superior type of void embedded SOI (VESOI) substrate. With the successful removal of most of the radiation sensitive area in buried oxide, the TID tolerance of VESOI MOSFET is significantly enhanced in comparison to its conventional SOI counterpart. In particular, the shift of threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> ) and subthreshold swing is only −38.9mV and 11.6mV/dec at radiation doses up to 2Mrad(Si). Further device simulation shows that the radiation immunity can withstand misalignment between the gate and embedded void in a wide range. Our VESOI substrates, offering both high compatibility with planar CMOS process and versatile void embedded device design, exhibit great potential in the development of anti-radiation SOI devices.