Abstract

2.1D package technology (chip on substrate) as a potential low cost solution for 2.5D silicon interposer package (chip on wafer on substrate), we develop here a panel type manufacture organic interposer (scheme 1). 2.1D technology focus on the production cost and the ball count range which defined by line/space. We presents the demonstration of high resolution photolithography semi-additive processes (SAP) to achieve 3 μm copper line widths and 25 μm laser drilled vias with panel-based processes by using large field projection lithography equipment and advanced dry film photoresists. Furthermore, electro-less copper plating seed layer (~0.1 μm) was chosen to replace sputtered metal seed layer. Compare to wafer pattering process, dry film photoresist and elctro-less copper seed layer processes can save significant equipment and material cost to reaches 3 μm level line width and gap. A metal layer redistribution layer (RDL) structure integrating high density lines and vias was demonstrated on 25 μm organic film. The organic interposer also consists of micro-bump pad of 25 μm diameter (40 μm pitch). The designed 2.1D organic interposer substrate has passed the reliability test with MSL3 (Moisture Soaking Level 3) standard and TCT (Thermal Cycling Test) 1000 cycles. The electrical performance of the substrate/organic interposer combination has also been tested.

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