Abstract
Scaling down of conventional flash memory technology faces difficult technical challenges and some physical limitations. Novel silicon-based flash cell structures were presented in this paper as possible solutions. A novel cell structure using dual doping polysilicon (PNP) as the floating gate is proposed and experimentally exhibit higher programming speed and better data retention characteristics in comparison with conventional n-type floating-gate structure. To further enhance storage density and relax the stringent requirements of scaling, a novel vertical channel dual-nitride-trapping-layer ROM (VDNROM) as a kind of SONOS flash is proposed and experimentally demonstrated. Compared with conventional planar NROM cell, VDNROM structure can have high capability of cell area shrinking and achieve four-physical-bit per cell storage capability. The fabrication technologies of the two novel devices are fundamentally compatible with standard CMOS process
Published Version
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