Novel Self-Timed, Pipelined Clock Scan Architecture

Abstract

In this paper, we describe a novel self-timed scan chain design approach to mitigate hold time and power supply noise problems during scan testing, and to simultaneously allow no delay penalty due to the front-end multiplexer in a multiplexer-D flip-flop (mux-DFF) scan cell. Hold time problems due to clock skew and static and dynamic power supply noise (i.e. IR drop and LdI/dt noise) due to simultaneous switching are two problems associated with shift operations during scan testing using ATPG patterns. These problems are particularly serious with mux-DFF style scan, and are either nonexistent or negligible with level-sensitive scan design (LSSD). This paper deals with a circuit technique to mitigate hold time, power supply noise and front-end delay penalty seen with mux-DFF and achieve a middle ground on clock routing overhead between LSSD and mux-DFF scan styles.