Novel modification in evanescent mode analysis to incorporate sub-1 nm equivalent oxide thickness in the subthreshold model of junctionless asymmetric double gate FETs

Abstract

A novel modification in the evanescent mode analysis is presented in this work to comprehend the implication of a high gate dielectric constant in the subthreshold model of junctionless (JL) asymmetric double gate (DG) FETs. A brief study is presented to highlight the lack of an appropriate device model for the JL FET with a sub-1 nm equivalent oxide thickness. This work elaborates the effect of a high-k gate dielectric on one of the most important parameters of evanescent mode analysis, known as the inverse characteristics length. Thereby, an appropriate modification is incorporated in the widely adopted evanescent mode analysis to develop the subthreshold model compatible with high-k gate-dielectric materials and sub-1 nm gate-oxide thickness. Subsequently, the subthreshold model of DG FET with a high-k gate dielectric is presented. The DG FET assumes gate-oxide asymmetry as well as channel doping asymmetry arising due to the ion-implantation and subsequent annealing. With the help of the developed model, the subthreshold characteristics of the device are studied with the variations in device dimensions, the gate-dielectric constant, the doping profile, etc. The results have been found to be in good agreement when numerically studied in comparison with the outcomes of the Synopsys Sentaurus™ Device simulation tool.