Novel CNFET ternary circuit techniques for high‐performance and energy‐efficient design

Abstract

Here, the authors propose a new family of ternary circuits for a general design perspective. Besides presenting an efficient ternary logical circuit approaches, the focus of this study is also about introducing techniques for reducing the performance metric cost of the proposed family. Basic ternary arithmetic gates, ternary half-adder, and ternary partial product generator are also proposed for two different levels. First, direct transistor level implementation is considered, next a modification in the gate level implementation representing a state-of-the-art approach is addressed. Carbon nanotube FET (CNFET) is considered as an appropriate technology for implementation and realisation of ternary circuits. Therefore, simulations are carried out at 32 nm CNFET model using Synopsis HSpice tool. Simulation results show the advantages of ternary structures considering the proposed method.