Novel capacitor process using diffusion barrier rounded by Si/sub 3/N/sub 4/ spacer for high density FRAM device

Abstract

A novel capacitor process was successfully implemented in 4 Mb FRAM device by developing a barrier layer rounded by Si/sub 3/N/sub 4/ spacer (BRS) scheme. Using this process, it is possible to eliminate an undesired barrier etching damage, which is a major role in degrading ferroelectric properties. The novel capacitor process was generated by etching an Ir barrier layer and rounding the barrier by a Si/sub 3/N/sub 4/ spacer before preparing Pb(Zr/sub 1-x/Ti/sub x/)O/sub 3/ (PZT) films. It was observed that uniform sol-gel derived PZT films were prepared on the patterned Ir substrate by using Si/sub 3/N/sub 4/ spacer, which provides a smooth edge of the patterned cell. The contact resistance between bottom electrode and polysilicon plug after full integration was monitored below 700 /spl Omega/ per contact with contact size 0.6/spl times/0.6 (/spl mu/m/sup 2/). Compared to the ferroelectric capacitor damaged by barrier etching, the novel Pb(Zr/sub 1-x/Ti/sub x/)O/sub 3/ (PZT) capacitor exhibited a well-saturated Q-V curve. The fully processed novel capacitor having 1.2/spl times/1.2 (/spl mu/m/sup 2/) effective area displayed remnant polarization of 14 (/spl mu/C/cm/sup 2/) at an operating voltage of 3.0 V. The BRS ferroelectric capacitor showed a reliable retention property until 100 h at 125/spl deg/C. Same state retention (Qss) was stable with time up to 100 h while opposite state retention (Qos) showed a log-linear decay rate at 125/spl deg/C thermal stress.