Abstract
Benes/Clos networks constitute a particularly important part of interconnection networks and have been used in numerous areas, such as multi-processor systems, data centers and on-chip networks. They have also attracted great interest in the field of optical communications due to the increasing popularity of optical switches based on these architectures. There are numerous algorithms aimed at routing these types of networks, with varying degrees of utility. Linear algorithms, such as Sun Tsu and Opferman, were historically the first attempt to standardize the routing procedure of this types of networks. They require matrix-based calculations, which are very demanding in terms of resources and in some cases involve backtracking, which impairs their efficiency. Parallel solutions, such as Lee’s algorithm, were introduced later and provide a different answer that satisfy the requirements of high-performance networks. They are, however, extremely complex and demand even more resources. In both cases, hardware implementations reflect their algorithmic characteristics. In this paper, we attempt to design an algorithm that is simple enough to be implemented on a small field programmable gate array board while simultaneously efficient enough to be used in practical scenarios. The design itself is of a generic nature; therefore, its behavior across different sizes (8 × 8, 16 × 16, 32 × 32, 64 × 64) is examined. The platform of implementation is a medium range FPGA specifically selected to represent the average hardware prototyping device. In the end, an overview of the algorithm’s imprint on the device is presented alongside other approaches, which include both hard and soft computing techniques.
Highlights
Communication between different integrated systems has been one of the cornerstones of technological advancement in the last decades
In the contemporary digital world, a sophisticated and complex structure ranging from data center (DC) servers to multicore processors are in need of fast and reliably functioning interconnection networks in order to attain maximum efficiency
We implemented the design on the mid-range FPGA board, ZCU-104 Evaluation board (Figure 13) using Vivado
Summary
Communication between different integrated systems has been one of the cornerstones of technological advancement in the last decades. In the contemporary digital world, a sophisticated and complex structure ranging from data center (DC) servers to multicore processors are in need of fast and reliably functioning interconnection networks in order to attain maximum efficiency. One such type of interconnection network that emerged from the Clos family [1] with. Benes networks are a well-known type of non-blocking multistage interconnection networks [3,4] They are rearrangeable and non-blocking [5], which practically means that all possible routing schemes (n!) can be satisfied if the entire network is reconfigured from the beginning every time there is a change in routing. It is a permutation network [2]
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have