Novel Analog Designs with Back-Gate Bias by Using Global Foundries 22FDX® Technology

Abstract

Designing in GlobalFoundries 22FDX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> technology (FD-SOI) is very similar to designing in bulk CMOS. However, it provides superior substrate isolation. The MOSFET conducting channels under the gate-oxide are isolated from the well or substrate by a thin insulating layer of buried oxide (BOX). It allows complete control of the channel and lowers junction capacitance. The threshold voltage (VT) of the device may be manipulated by a combination of device type and well type to raise or lower the device threshold voltage. PMOS in Pwell and NMOS in Nwell may be used to achieve super low VT, while NMOS in Pwell and PMOS in Nwell may be used to increase VT, typically for applications demanding low leakage. Advantages include Enhanced mobility, less sensitivity to layout dependent effect (LDE) such as LOD (Length Of Diffusion), OSE (OD Space Effect), WPE (Well Proximity Effect), etc., and excellent device matching. This paper will present analog applications of back gate biasing and other 22FDX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> technology features that will improve PPA (power, performance and area).