Novel 8T Bit-cell with High RSNM for Sub-threshold SRAM

Abstract

Since the sub-threshold circuit technology was widely applied to SRAM circuit, the power supply voltage was greatly reduced, and then, the performance of environmental parameters and process deviations on sub-threshold circuit become critical. The changes in environmental parameters and process deviations easily make traditional 6T SRAM circuit lead to fatal errors, particularly, the Read Static Noise Margin (RSNM) is deteriorated obviously. In order to improve the performance of RSNM, we proposed a novel 8T SRAM bit-cell which uses the read and write separation structure and Partial Dynamic Threshold voltage (PDT) technology. This paper firstly introduces the PDT technology and read and write separation structure; then proposes the novel 8T structure and explains the operating principle of the 8T bit-cell; finally gives the result of the simulation for the stability performance of the 8T bit-cell compare to other 3 kinds of 6T bit-cell. The comparison results show that the proposed 8T bit-cell greatly improves the RSNM of the SRAM bit-cell.