Abstract
The need for fastest addition techniques is ramping with trends in digital system architectures. This paper presents the architecture of novel N-bit Statistical carry look ahead adder which attains high operating speed with low power and low transistor count by incorporating the 2:1 MUX and NMOS adder techniques The 2:1 MUX is having the advantage of reduced decision making and the NMOS technique will exploit the advantages of switch. The new techniques will achieve the average addition time less than log2(N). The proposed N-Bit adder was realized with Cadence design tools in 180, 90 and 45 nm processing technologies with supply voltages 1.8, 1 and 1 v respectively. The proposed 2:1 MUX and NMOS techniques are 10.9 and 63 % respectively compared to the conventional SCLA. And also achieving low power dissipation.
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