A Proposed Work for Reduction Of Power In Level Shifter

Abstract

The growing urge of VLSI technology to exhibit low power and high speed operating devices has always led to the need of devices that operate at multiple voltage domains. In order to incorporate this multiple voltage devices on a single VLSI chip, the level shifter forms an essential circuit. This power domain issue is more prominent in the devices exhibiting sub-threshold operations. Thus designing a level shifter plays a crucial role especially in the design of complex circuits that have multi-voltage domains. The major challenges in the design of level shifters are low power dissipation, transistor count, high performance and robustness. This paper focuses on an attempt to change the circuit in order to get low power dissipation. Multiple Threshold Level Shifter (MTLS) that incorporates transistors with different threshold voltages within the circuit. Compared to the existing Differential cascode voltage switch (DCVS) logic, the power delay product (PDP) of MTLS is found to be efficient. Thus MTLS could be used to cascade complex circuits.