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Abstract
Notice of Violation of IEEE Publication Principles<br><br>"Study of Fault-Tolerant Routing Algorithm of NoC Based on 2D-Mesh Topology"<br> by Shu Yan Jiang, Yue Liu, Jiang Bo Luo, He Cheng, and Gang Luo in the Proceedings of IEEE International Conference on Applied Superconductivity and Electromagnetic Devices, October 2013, pp. 189-193<br><br> After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.<br><br> This paper copied portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.<br><br> "A Fault-Tolerant and Hierarchical Routing Algorithm for NoC Architectures"<br> by Mojtaba Valinataj, Pasi Liljeberg, and Juha Plosila<br> in the Proceedings of NORCHIP 2011, November 2011<br><br> <br/> Since various software errors or hardware failures may destroy the transfer data of Network-on-Chip (NoC), it is essential to study the fault-tolerant methods of NoC. Based on the original XY Dimension Order Routing algorithm, this paper improved the single link failure tolerance, by reconfiguration and defining a new deterministic routing algorithm for all routers on a cycle-free contour around a faulty link to replace the broken paths with new unique paths. Then we gave the follow-up improvement ideology for link failures and router fault tolerance. Finally, it proved that the design of the routing algorithm can successfully avoid all six kinds of single link failures, and the fault-tolerant algorithm was verified on the ISE platform to proved to be reliable and effective. Thanks to the algorithm does not require virtual channels, the area and power consumption will be reduced.
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