Notice of Violation of IEEE Publication Principles - New architecture of low voltage sigma-delta ADC

Abstract

A low voltage low power sigma delta modulator was presented. A sigma delta modulator architecture which was very adapt to low voltage low power applications was proposed. With the advantage of both unity gain sigma delta modulator and traditional sigma delta modulator, it relaxed the requirement of the OTA performance and decreased the complex of the circuit. For lower power consumption as soon as possible, the technique of negative resistance load was used to improve the dc gain of the current mirror OTA and the technique of Class-AB output stage was used for lower power consumption. Simulation results showed that with 0.18 um CMOS technology, 20 KHz signal bandwidth and oversampling rate of 156, the modulator achieved 93 dB dynamic range, the power consumption was 500 uW under 1 V supply voltage and the chip core size was 0.5 mm2. Measure results showed that with 2 MHz sampling frequency and 1 KHz input signal the sigma delta modulator achieved 65 dB SNR and 60 dB SNDR.