Abstract
In this paper, a low power sigma delta modulator with dynamic biasing technique is presented. According to the analysis of the operations of the switched-capacitor integrator, the folded-cascode operational amplifier can be designed with optimized biasing currents in three different phases to reduce power dissipations. The total power saving is 20% of the general one. A prototyping fourth order single-bit MASH 2-2 sigma delta modulator is designed with the technique of dynamic biasing to achieve dynamic range of 95dB and peak signal-to-noise-and-distortion-ratio of 93dB. The experimental circuit is designed in 0.35μm 2P4M CMOS technology. The chip area is 3.11mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the power dissipation is only 5mW from a supply voltage of 3V.
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