Nonvolatile Charge-Trap Memory Transistors With Top-Gate Structure Using In–Ga–Zn-O Active Channel and ZnO Charge-Trap Layer

Abstract

We proposed a charge-trap-type memory transistor with a top-gate structure composed of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> blocking/ZnO charge-trap/IGZO active/ Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> tunneling layer. The memory ON/OFF ratio higher than six-orders-of magnitude was obtained after the programming when the width and amplitude of program pulses were 100 ms and ±20 V, respectively. Excellent endurance was successfully confirmed under the repetitive programming with 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> cycles. The memory ON/OFF ratio higher than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> was guaranteed even after the lapse of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s. Interestingly, the retention properties were affected by the bias conditions for read-out operations.