Non-preemptive test scheduling for Network-on-Chip(NoC) based systems by reusing NoC as TAM

Abstract

Network-on-Chip (NoC) is becoming a promising communication architecture for the next generation embedded cores based system chips. The reuse of NoC as test access mechanism (TAM) for the embedded cores reduces the test time of the system. However, NoC reuse is limited by the on-chip routing resources and some other constraints. Therefore, efficient test scheduling methods are required to provide feasible test time, opening with other constraints. In this paper we have proposed the non-preemptive test scheduling approach based on Genetic Algorithm (GA) formulation. Experimental results with the ITC'02 System-on-Chip(SOC) test benchmarks show that GA produces scheduling of cores with 33% lesser overall test time of the system compared to the method proposed in the literature.