Abstract
The flip-flop is one of the most important parts of sequential logic circuits. The design of a structure with a smaller size and less delay is of great importance. This paper presents a new structure for T flip-flop using a multiplexer. Also, a new structure for the edge-to-level converter has been proposed in a creative way, based on the Coulomb interaction between cells. Finally, using these structures, a new three-layer structure for the synchronous counter is presented. In this design, in addition to designing structures with fewer cells, three-layer methodology has been used, which has a significant effect on reducing the size of the circuit. The simulation results show the superiority of the proposed synchronous counter in terms of cell reduction of 35% and area reduction of 66% compared to previous one. It also provides 11% improvement in clock zones.
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