Abstract
Introduction Cleaning is required following CMP (chemical mechanical planarization) to remove particles as well as metallic and organic contamination. Particle and contamination requirements tighten with each successive technology generation, and the cleaning of wafers becomes more complicated and more critical [1]. Smaller size particles must be removed from the wafer surface as linewidths decrease while lower and lower contamination levels must be achieved as device electrical parameters tighten. Metal contamination on the dielectric surface may cause dielectric leakage and any metals that affect the electrical properties of silicon must be removed from the surface. In addition, constraints on the aggressive nature of the cleaning process are increased. For example, the amount of material removed in the cleaning process and the resulting surface roughness must be precisely controlled.
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