Noise Immunity Improvement in Dynamic CMOS circuits

Abstract

For the purpose of high system performance dynamic CMOS circuits are widely use in high performance VLSI chips. But dynamic CMOS gates are found to be less noise resistant then static CMOS gates. Due to aggressive technology scaling, stringent noise requirement has been increased, hence the noise tolerance of dynamic circuits has to be first improved for the over all reliable operation of VLSI chip. A new technique (Transparency window technique) which increases the noise immunity with the precharge of one internal node of N‐logic and isolating the precharge dynamic node‐and consequently the output from the inputs during the evaluation phase, is introduced to improve the noise tolerance of digital circuits. Simulation result on Pspice 9.1 and 0.65 μm technology shows that this technique improves noise immunity of the dynamic circuits as compared to conventional and previous noise tolerance technique.