Abstract
A new level shift circuit featuring with capacitive load instead of resistive load is proposed and investigated in this paper. The proposed design can help the high voltage gate drive integrated circuit (HVIC) to achieve the high d Vs/dt noise immunity up to 85 V/ns and the allowable negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> swing to -12 V at 15 V supply voltage. The temperature characteristic of the above reliability items of the HVIC with the proposed capacitive-loaded level shift (CLLS) circuit are investigated for the first time and are an improvement when compared to those of the conventional resistive-loaded level shift circuit, which is verified by numerous theoretic analyses and experiments. Moreover, although four high voltage lateral double-diffused metal-oxide-semiconductor transistors are used in the proposed CLLS circuit, no extra chip size is needed due to the fact that the transistors can be embedded in the high voltage isolation structure base on 0.5 μm Bipolar-CMOS-DMOS technology.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
