Abstract
In this paper we explore the noise and linearity limitations of a delay line based frequency to voltage converter (FVC) for use in an analog to digital converter (ADC) linearization system. Phase noise due to the delay line is the main source of noise in the FVC. In this paper we derive the relationship between the phase noise and the output voltage noise of the FVC. Furthermore, we characterize the constraints on the design of the delay line to ensure good linearity and derive a relationship between the series resistance of the buffer driving the output filter and the total harmonic distortion (THD). Simulation results obtained using a commercially available 90 nm process design kit (PDK) show good agreement between the predicted noise and linearity and the simulated results.
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