Noise and Energy Consumption Analysis of SAR and SAR-Pipelined ADCs

Abstract

This paper presents a comparison between a successive approximation register (SAR) analog-to-digital converter (ADC) and a 2-stage SAR-pipelined ADC in terms of noise and energy consumption. The goal is to explore the trade offs among both architectures and to determine which topology is more efficient according to a target effective number of bits (ENOB). The SAR-pipelined ADC is implemented with 1-bit redundancy to avoid over-range in the second stage. Non-ideal residue amplifier gains are also taken into account in this analysis. System level simulations demonstrate that to achieve an ENOB higher than 8.5 bits the SAR-pipelined ADC is more efficient than SAR topology, while for ENOBs lower than 8.5 bits the SAR ADC is preferred.