NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology

Abstract

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/L/sub npn/ protection devices in a 0.13-/spl mu/m CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 /spl mu/m) devices fail because of source/drain filamentation, whereas longer (0.3 /spl mu/m) devices with thin (22 /spl Aring/) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on I/sub t2/. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device.