Next Generation Test Generator (NGTG) interface to Automatic Test Equipment (ATE) for digital circuits

Abstract

Although current methods for digital and analog circuit testing in the NAVY Automatic Test Equipment (ATE) environment are adequate, there are limitations and pitfalls. These can be due to inadequate transfer of information between the design and test of a circuit card resulting in untestable circuits. This can lead to expensive and time consuming test generation. Next Generation Test Generator (NGTG) has developed a process that will generate tests and diagnostic data using genetic algorithms and neural networks. This paper describes the procedure that will be used to interface NGTG and the ATE. NGTG will be demonstrated on Consolidated Automated Support System (CASS). For digital circuit testing, the CASS environment uses the Digital Test Unit (DTU). This environment requires diagnostic data in a unique language, L200, to process information. The NGTG system must interface with the DTU via Abbreviated Test Language for All Systems (ATLAS) code. ATLAS uses a Functional External Program (FEP) to interface with the DTU. This paper will describe the two options and the necessary steps to demonstrate NGTG on CASS. These options involve diagnostic data in the proposed IEEE-P1445 Standard, Digital Test Interchange Format (DTIF) formatted files and new NGTG/FEP interfaces.