Next generation of Deep Trench Isolation for Smart Power technologies with 120 V high-voltage devices

Abstract

A new Deep Trench Isolation (DTI) structure with high-voltage capability (BV > 150 V) and latch-up suppression (log( I c/ I e) < −2 in adjacent pockets) is experimentally demonstrated in this work. The new DTI is implemented in a Nepi/BLN/N −/P + Silicon stack by using a 0.18 μm CMOS-based platform. Moreover the advantages and design limitations of the new DTI are investigated by TCAD simulations and analytical models, being compared to its DTI predecessor in a Nepi/BLN/P −/P + stack.