MOS Capacitor Deep Trench Isolation for CMOS image sensors

N Ahmed,D Pellissier-Tanon,G-N Lu,N Virollet,M Rivoire,F Roy,B Mamdy,A Seignard,F Leverd,A Tournier,B Orlando,C Perrot,J-P Carrere

doi:10.1109/iedm.2014.7046979

MOS Capacitor Deep Trench Isolation for CMOS image sensors

N Ahmed, D Pellissier-Tanon + Show 11 more

https://doi.org/10.1109/iedm.2014.7046979

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Publication Date: Dec 1, 2014

Citations: 18

Affiliation: STMicroelectronics (France), Institut des Nanotechnologies de Lyon, French National Centre for Scientific Research, CEA Grenoble, CEA LETI, Atomic Energy and Alternative Energies Commission

#Deep Trench Isolation #High Full-well Capacity + Show 8 more

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Abstract

This paper proposes the integration of MOS Capacitor Deep Trench Isolation (CDTI) as a solution to boost image sensors' pixels performances. We have investigated CDTI and compared it to oxide-filled Deep Trench Isolation (DTI) configurations, on silicon samples, with a fabrication based on TCAD simulations. The experiment measurements evaluated on CDTI without Sidewall Implantation (SWI) exhibit very low dark current (∼1aA at 60°C for a 1.4µm pixel), high full-well capacity (∼12000e-), and it shows quantum efficiency improvement compared to DTI configuration. Pixels with optimized CDTI gate oxide thickness have demonstrated comparable angular response to oxide-filled DTI counterparts.

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