New PEC optimization for the mask fabrication of sub-50nm memory device

Abstract

The tight MTT control is required for the mask process of sub-50nm design node due to the complex OPC and insufficient process margin. The MTT below 5nm is already required for the critical layers. Below 4nm is required for sub-50nm node. In the viewpoint of this requirement, the MTT control is important for the mask fabrication. According to the shrinking design node, the linearity is the main issue to satisfy MTT required. In the electron beam (ebeam) lithography, the linearity results are strongly related to the resolution of the mask process. Isolated and dense patterns have the different linearity behaviors due to the different contrast mainly caused by the backward scattering contribution and develop process. Because of this reason, the conventional method of proximity effect correction (PEC) optimization is unlikely to satisfy the MTT requirement. New PEC optimization is necessary for sub-50nm node. In this report, new PEC optimization method is proposed. This method reduces the PEC error of conventional optimization method known as a few nm. Because of the linearity, the error of conventional PEC optimization is amplified according to the shrinking design. Therefore, the PEC error of conventional method is larger than the MTT requirement for sub-50nm node. This new method is designed to overcome this problem. It takes into account for the properties of each layer. Based on the analysis of composition of each layer, the different PEC optimization to fit the each layer and design node is applied. It is able to be applied for the mask fabrication of sub-50nm memory device. The improvement of MTT is achieved by the reduction of the PEC error with new PEC optimization.