New optimal error-correcting codes for crosstalk avoidance in on-chip data buses

Abstract

<p style='text-indent:20px;'>Codes that simultaneously provide for low power dissipation, cross-talk avoidance, and error correction in the ultra deep submicron/nanometer VLSI fabrication, were recently introduced by Chee et al. in 2015. Such codes were revealed to be closely related to balanced sampling plans avoiding adjacent units, which are widely used in the statistical design of experiments. In this paper, we construct a new family of optimal codes with such properties, by determining the maximum size of packing sampling plans avoiding certain units.