New observation on gate-induced drain leakage in Silicon nanowire transistors with Epi-Free CMOS compatible technology on SOI substrate

Abstract

As a promising transistors beyond 22nm technology node, Silicon nanowire (Si NW) transistor has attracted a lot of attentions recently [1]-[4]. Due to its unique gate-all-around (GAA) structure, Si NW transistor provides enhanced gate controllability and reduced sub-threshold leakage. However, gate-induced drain leakage (GIDL) as another primary leakage mechanism is still challenging [5][6]. In addition, due to the lateral parasitic bipolar junction transistor (PBJT), GIDL can be further enhanced in floating body transistors including Si NW transistor [7]. Unfortunately, few work on the origin sources and mechanism of GIDL in Si NW transistors have been reported up to now. In this paper, we have successfully fabricated Si NW transistors of high driving current with diameter down to 10nm on SOI substrate. More serious GIDL at low |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> | in Si NW transistor is observed compared with planar devices, which results from the strong gate-controlled longitudinal band-to-band tunneling (L-BTBT) of Si NW transistor, rather than traditional vertical BTBT in planar device. The dependence of GIDL on geometry parameters is also evaluated for further optimization.