Investigation of gate-all-around silicon nanowire transistors for ultimately scaled CMOS technology from top-down approach

Abstract

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the key issues regarding SNWTs from the top-down approach including process integration, carrier transport, and fluctuation and variability in these unique one-dimensional stronglyconfined nanowire devices. A new process integration scheme for SNWTs is discussed, which features a fully-Si-bulk substrate, an epi-free process, a self-aligned structure and a large source/drain fan-out. The physical characteristics of the fabricated devices with 10-nm-diameter nanowires are further investigated. The carrier transport performance in SNWTs is experimentally estimated, with a modified extraction methodology which takes into account the impact of temperature dependence of parasitic source resistance. SNWTs with sub-40-nm gate lengths exhibit high ballistic efficiency at room temperature, indicating great potential for SNWTs as an alternative device structure for near-ballistic transport. For heat transfer in SNWTs, the self-heating effect is also characterized. However, due to the one-dimensional (1-D) nature of nanowires and increased phonon-boundary scattering in the GAA structure, the self-heating effect in SNWTs based on the bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus, special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally studied in detail. The results of extracted variation sources indicate that, with suppressed random dopant fluctuations in the intrinsic channel, variations in radius and metal-gate work function of SNWTs dominate both the threshold voltage and on-current fluctuations. Comparing with conventional planar MOS devices, SNWT based SRAM cells exhibit better stability due to the superior electrostatic control in SNWTs.