New Negative-Bias-Temperature-Instability Improvement Using Buffer Layer under Highly Compressive Contact Etch Stop Layer for 45-nm-Node Complementary Metal–Oxide–Semiconductor and Beyond

Abstract

A remarkable 50% drive current enhancement for p-type metal–oxide–semiconductor field-effect-transistors (pMOSFETs) using a highly compressive SiN contact etch stop layer (CESL) has been successfully demonstrated. In this study, we also first proposed that applying a modulated buffer layer prior to the highly compressive CESL could significantly improving negative-bias-temperature-instability (NBTI) and time-dependent-dielectric-breakdown (TDDB) degradation of pMOSFETs using compressive CESL. Without adversely impact the significant drive current enhancement of pMOSFETs, this thin modulated buffer layer can improve the NBTI lifetime of core pMOSFETs by over two orders of magnitude. Instead of the complex and high-costly SiGe refill scheme, this highly compressive CESL layer with a thin modulated buffer layer successfully demonstrates a better candidate for pMOSFETs drive current enhancement of 45-nm-node CMOS and beyond.