New Models of Prefix Adder Topologies

Abstract

This paper introduces a variety of approaches for assessing logarithmic-depth parallel prefix adders: a delay model based on a slight modification to the Logical Effort methodology is derived; a simple area model based on wire pitch is described; a new parameter, span(i), is defined that provides a mechanism for determining cell count and whether a prefix tree exhibits idempotency. The models are tested against Knowles' Family of Adders and found to give results that are within 5% of those reported by Knowles, as well as allowing a full assessment of the family to be made. Finally, the delay and area models are used to assess the Flagged Prefix Adder, an enhanced adder capable of computing absolute differences.