Abstract
High performance power device is required to develop efficient and smart power management integrated circuits. A novel Lateral Double Diffused MOSFET (LDMOS) structure having partially counter doped region in STI edge area of drift region is proposed. Due to Reduced Surface Field (RESURF) effect induced by partially counter doped region, lower gate to drain overlap capacitance C GD , which is able to reduce dynamic power consumption through increasing switching speed due to Miller capacitance load reduction in circuit operation, and better BVD SS -R ON characteristics can be achieved in new LDMOS structure. This structure can be easily realized through only adding one additional counter doping implant step in drift implant stage without any additional mask layers or process modifications in conventional LDMOS structure. Technology Computer Aided Design (TCAD) analysis results clearly show that Miller capacitance C GD can be significantly reduced with big improvement in breakdown characteristics. These distinct advantages in electrical performance can help to enhance high-frequency performance and reduce power loss in power application circuits.
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