Abstract
Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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